In processor designs which use a cache memory architecture, overall performance can be greatly improved by prefetching instructions from a bulk storage unit and placing then in a cache memory prior to the time the processor will be using them. This is easily accomplished with program instructions since they are sequential in nature. The sequential nature of program instructions allows a memory controller to prefetch a group of instructions and load them into a cache line based simply on the current instruction address. Prefetch mechanisms for data do not work very well since data, unlike program instructions, is generally not sequential in nature or arranged in the order the program will access it.